Position Overview: We are looking for a highly skilled FPGA Verification Engineer who will be responsible for verifying the functionality and performance of our FPGA designs. The ideal candidate will have a strong background in digital design, verification methodologies, and FPGA development.
Key Responsibilities:
- Develop and execute comprehensive verification plans for FPGA designs to ensure functionality, performance, and compliance with specifications.
- Design and implement verification test benches using industry-standard tools and methodologies such as UVM, SystemVerilog, and VHDL.
- Develop reusable verification components and test cases to improve verification efficiency and coverage.
- Collaborate closely with the design team to understand design requirements and identify potential issues early in the development cycle.
- Debug and resolve verification failures, and work closely with the design team to implement necessary fixes.
- Perform functional simulations, timing simulations, and gate-level simulations to validate FPGA designs.
- Analyze and optimize verification methodologies to improve efficiency and reduce verification time.
- Stay current with the latest developments in FPGA technology, verification methodologies, and industry trends.
Qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. Master's degree preferred.
- Solid understanding of digital design fundamentals and FPGA architecture.
- Proficiency in verification methodologies such as UVM, SystemVerilog, and VHDL.
- Experience with FPGA development tools such as Vivado, Quartus, or Libero.
- Strong programming skills in languages such as Verilog, SystemVerilog, and C/C++.
- Experience with scripting languages such as Python, Tcl, or Perl for automation tasks.
- Excellent problem-solving and debugging skills.
- Strong communication and teamwork skills, with the ability to collaborate effectively with cross-functional teams.
